Into the Void: x86 Instruction Set Reference

Opcode	Mnemonic	Description
`F3 0F 5E /r`	`DIVSS xmm1, xmm2/m32`	Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2/m32.

Description
Divides the low single-precision floating-point value in the destination operand (first operand) by the low single-precision floating-point value in the source operand (second operand), and stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of a scalar single-precision floating-point operation.

Operation
Destination[0..31] = Destination[0..31] / Source[0..31]; //Destination[32..127] remains unchanged

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#NM

If TS in CR0 is set.

#XM

If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD

If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.

Instruction	Latency	Throughput	Execution Unit
`CPUID`	0F3n/0F2n	0F3n/0F2n	0F2n
`DIVSS xmm, xmm`	32/23	32/23	FP_DIV

x86 Instruction Set Reference