Sun: x86 Instruction Set Reference

Opcode	Mnemonic	Description
`F2 0F 5E /r`	`DIVSD xmm1, xmm2/m64`	Divide low double-precision floating-point value n xmm1 by low double-precision floating-point value in xmm2/mem64.

Description
Divides the low double-precision floating-point value in the destination operand (first operand) by the low double-precision floating-point value in the source operand (second operand), and stores the double-precision floating-point result in the destination operand. The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. The high quadword of the destination operand remains unchanged. See Figure 11-4 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of a scalar double-precision floating-point operation.

Operation
Destination[0..63] = Destination[0..63] / Source[0..63]; //Destination[64..127] remains unchanged

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#NM

If TS in CR0 is set.

#XM

If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD

If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Instruction	Latency	Throughput	Execution Unit
`CPUID`	0F3n/0F2n/069n	0F3n/0F2n/069n	0F2n
`DIVSD xmm, xmm`	39/38/32	39/38/31	FP_DIV

x86 Instruction Set Reference