x86 Instruction Set Reference

CVTSD2SS

Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value

Opcode Mnemonic Description
F2 0F 5A /r CVTSD2SS xmm1, xmm2/m64 Convert one double-precision floating-point value in xmm2/m64 to one single-precision floating-point value in xmm1.
Description

Converts a double-precision floating-point value in the source operand (second operand) to a single-precision floating-point value in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register. The result is stored in the low doubleword of the destination operand, and the upper 3 doublewords are left unchanged. When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
Operation 
Destination[0..31] = ConvertDoubleToFloat(Source[0..63]);
//Destination[32..127] remains unchanged
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#NMIf TS in CR0 is set.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UDIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
Real-Address Mode Exceptions
#GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
#GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NMIf TS in CR0 is set.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode
#PF(fault-code)For a page fault.
#PF(fault-code)For a page fault.
Instruction Latency Throughput Execution Unit
CPUID0F3n/0F2n/069n0F3n/0F2n/069n0F2n
CVTSD2SS xmm, xmm17/16/42/4/1FP_ADD MMX_SHFT