x86 Instruction Set Reference

CVTDQ2PD

Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values

Opcode Mnemonic Description
F3 0F E6 CVTDQ2PD xmm1, xmm2/m64 Convert two packed signed doubleword integers from xmm2/m128 to two packed double-precision floating-point values in xmm1.
Description

Converts two packed signed doubleword integers in the source operand (second operand) to two packed double-precision floating-point values in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the packed integers are located in the low quadword of the register.
Operation 
Destination[0..63] = ConvertIntegerToDouble(Source[0..31]);
Destination[64..127] = ConvertIntegerToDouble(Source[32..63]);
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#NMIf TS in CR0 is set.
#UDIf EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
Real-Address Mode Exceptions
GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NMIf TS in CR0 is set.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode
#PF(fault-code)For a page fault.
#PF(fault-code)For a page fault.
Instruction Latency Throughput Execution Unit
CPUID0F3n/0F2n/069n0F3n/0F2n/069n0F2n
CVTDQ2PD xmm, xmm8/8/43/3/4FP_ADD MMX_SHFT