Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s. The destination operand may be an MMX technology register or an XMM register; the count operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate.

The PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits specified in the count operand; the PSRLD instruction shifts each of the doublewords in the destination operand; and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.

switch(Instruction) {
	case PSRLW:
		if(OperandSize == 64) {
			//PSRLW instruction with 64-bit operand:
			if(Count > 15) Destination[64..0] = 0;
			else {
				Destination[0..15] = ZeroExtend(Destination[0..15] >> Count);
				Destination[16..31] = ZeroExtend(Destination[16..31] >> Count);
				Destination[32..47] = ZeroExtend(Destination[32..47] >> Count);
				Destination[48..63] = ZeroExtend(Destination[48..63] >> Count);
			}
		}
		else {
			//PSRLW instruction with 128-bit operand:
			if(Count > 15) Destination[128..0] = 0;
			else {
				Destination[0..15] = ZeroExtend(Destination[0..15] >> Count);
				Destination[16..31] = ZeroExtend(Destination[16..31] >> Count);
				Destination[32..47] = ZeroExtend(Destination[32..47] >> Count);
				Destination[48..63] = ZeroExtend(Destination[48..63] >> Count);
				Destination[64..79] = ZeroExtend(Destination[64..79] >> Count);
				Destination[80..95] = ZeroExtend(Destination[80..95] >> Count);
				Destination[96..111] = ZeroExtend(Destination[96..111] >> Count);
				Destination[112..127] = ZeroExtend(Destination[112..127] >> Count);
			}
		}
		break;
	case PSRLD:
		if(OperandSize == 64) {
			//PSRLD instruction with 64-bit operand:
			if(Count > 31) Destination[64..0] = 0;
			else {
				Destination[0..31] = ZeroExtend(Destination[0..31] >> Count);
				Destination[32..63] = ZeroExtend(Destination[32..63] >> Count);
			}
		}
		else {
			//PSRLD instruction with 128-bit operand:
			if(Count > 31) Destination[128..0] = 0;
			else {
				Destination[0..31] = ZeroExtend(Destination[0..31] >> Count);
				Destination[32..63] = ZeroExtend(Destination[32..63] >> Count);
				Destination[64..95] = ZeroExtend(Destination[64..95] >> Count);
				Destination[96..127] = ZeroExtend(Destination[96..127] >> Count);
			}
		}
		break;
	case PSRLQ:
		if(OperandSize == 64) {
			//PSRLQ instruction with 64-bit operand:
			if(Count > 63) Destination[64..0] = 0;
			else Destination = ZeroExtend(Destination >> Count);
		}
		else {
			//PSRLQ instruction with 128-bit operand:
			if(Count > 15) Destination[128..0] = 0;
			else {
				Destination[0..63] = ZeroExtend(Destination[0..63] >> Count);
				Destination[64..127] = ZeroExtend(Destination[64..127] >> Count);
			}
		}
		break;
}

None.